1. Field of the Invention
This disclosure relates to a test kit for a semiconductor package, and more particularly, to a head assembly and a socket used in testing a semiconductor package.
2. Description of the Related Art
In order to decrease the thickness and the size of semiconductor packages, semiconductor packages using solder balls instead of leads as an external connection terminal, for example, a micro ball grid array (micro BGA) package and a chip scale package (CSP) have been developed.
Generally, the characteristics of semiconductor devices are tested several times during manufacturing using a PC tester including several instruments. Examples of an electrical test of the semiconductor devices using such a tester include an electrical die sorting (EDS) conducted at wafer level, a final test conducted after the assembly of the semiconductor packages has been completed, and reliability tests of semiconductor chips at wafer level and semiconductor packages conducted after the assembly of the semiconductor packages has been completed.
Further, examples of the final test include a room temperature electrical final test, a cold temperature electrical final test conducted at a temperature lower than the room temperature, and a hot temperature electrical final test conducted at a temperature higher than the room temperature. Also, a burn-in test is an inspection for judging whether the semiconductor devices are usable after a high temperature and a high voltage are applied thereto in order to detect possible defective semiconductor devices. That is, the semiconductor devices presenting a highly defective possibility are preliminarily eliminated before shipped to a customer.
The EDS test of the semiconductor devices using the tester is classified into a serial test and a parallel test. In the serial test, one semiconductor package is tested at a time, while in the parallel test, a large number of semiconductor chips or a large number of semiconductor packages are tested simultaneously and bulk-tested.
Since 32-256 sockets are mounted in one interface board used in the burn-in test and in the parallel test, a large number of the semiconductor chips or a large number of the semiconductor packages can be tested simultaneously and bulk-tested through the -in test and the parallel test.
FIG. 1 is a plan view illustration of a socket contact board 20 of a socket in which an adapter is mounted in a test kit for a semiconductor package according to a prior art, and FIG. 2 is a cross-sectional view illustration for explaining the loading of the semiconductor package using the socket contact board 20 of FIG. 1.
Specifically, FIGS. 1 and 2 show the socket contact board 20 included in a socket of an interface board used in a micro BGA package or a CSP using solder balls as an external connection terminal. In the socket contact board 20, a number of socket pins 34, which are in one-to-one correspondence with external connection terminals 32 of a semiconductor package 30, are arranged in an array pattern. An adapter 41 matching the size of a body of the semiconductor package 30 is installed on the socket contact board 20 through fixators 42.
Since the adapter 41 has an inclined surface 40 formed inside thereof, the package body sliding along the inclined surface 40 is positioned in the adapters 41 and is correctly loaded on the socket contact board 20. Thus, the external connection terminals 32 are correctly connected to the socket pins 34 of the socket contact board 20.
In order to mount as many as possible semiconductor chips in one wafer, research on reducing the size of the semiconductor chips has been continuously carried out. A reduction in the size of the semiconductor chips implies a reduction in the size of the semiconductor packages. For example, in a case where the size of the package body is reduced as indicated by a dotted line 50 in FIG. 1, it is difficult to use the conventional adapter 41 due to a difference in size between the adapter 41 and the reduced package body. That is, the external connection terminals 32 and the socket pins 34 are not correctly connected when the small-sized semiconductor package 30 is loaded on the socket contact board 20. Thus, if the size of the semiconductor package 30 changes, a new adapter is indispensably needed.
FIG. 3 is a plan view illustration of the socket contact board 20 for explaining the use of a newer adapter 41A to accommodate a change in the size of the semiconductor package.
As shown in FIG. 3, in a case where the size of the package body and an array pattern of solder balls used as an external connection terminal changes greatly, the adapter 41A whose shape is modified to be suitable for the modification of the semiconductor package is attached to the package body using fixators 42, and then an electrical test is conducted on the semiconductor package. That is, in this case, the new adapter 41A is indispensably needed in the electrical test.
Also, in a case where a parallel test or a -in test is conducted on the semiconductor package, a large number of the interface boards are required to be newly manufactured or exchanged, even if the shape of the semiconductor package slightly changes. As a result, the cost needed for testing the semiconductor package increases.
Further, if the size of the package body changes, a new adapter die must be manufactured and the existing adapters must be removed from a large number of the sockets mounted in one interface board and exchanged with new adapters. Further, since separate interfaces boards are needed with respect to each of the semiconductor packages, efficiency in a process for testing the semiconductor package is reduced.
Embodiments of the invention address these and other limitations in the prior art.